The invention relates in particular to thinned semiconductor wafers and thinned semiconductor chips, as are described in patent application DE 10 2004 054 147. Thinned semiconductor wafers and thinned semiconductor conductor chips such as these are used for power diodes, field-effect power transistors and other semiconductor components, in order, for example, to reduce the on-state resistance. In addition, thinned semiconductor wafers and thinned semiconductor chips such as these are also used for semiconductor modules, in order to drastically reduce the semiconductor component height.
Both in manufacture and in handling, these thinned semiconductor wafers and thinned semiconductor chips are considerable disadvantages, since they are mechanically at risk and must nevertheless be provided with wiring structures on their upper faces and with contact layers on their rear faces. As described in patent application DE 10 2004 054 147, the semiconductor wafers and semiconductor chips are fixed on intermediate mounts for manufacture and for handling, in order to absorb the loads which occur during handling and manufacture.
One disadvantage of fixing on an intermediate mount is the additional manufacturing effort for fitting and removal of the intermediate mount, which may be associated not only with contamination of the high-purity semiconductor material with contaminants through the material of the intermediate mount, but is also associated with an increased risk of fracture of the thinned semiconductor wafer or the thinned semiconductor chip.
Furthermore, one disadvantage of semiconductor wafers and semiconductor chips, in particular for power applications, is that a metallic wiring structure may be required on the semiconductor wafer or on the semiconductor chips, in order to commit the integrated circuit close to the surface to external contacts of the semiconductor component. Wiring structures such as these are provided by metals, which decrease the thermal operating range of the semiconductor elements, since they have a tendency to migration and to reaction with the semiconductor material, so that the theoretical limit of the thermal load capacity of a semiconductor material such as silicon is not reached. In addition, thermal process steps after metallization are restricted to low temperatures.
Finally, after metallization, the semiconductor wafers and the semiconductor chips are provided on their surfaces with a passivation layer or protective layer, which is deposited from the gas phase at low temperatures. Owing to the limited thermal load capacity of the metallic wiring layers on a semiconductor wafer or a semiconductor chip, passivation layers such as these, which are deposited at low temperatures, do not have a high density, and thus are not sufficiently thermally stable, so that the reliability of the semiconductor components in the case of semiconductor wafers and semiconductor chips with passivation layers such as these is decreased.